Electromagnetic interference (EMI) originating from high frequency applications is a problem that increases with the multiplication of wireless services and devices. Shielding is the conventional approach to counteract EMI; however, it requires considerable investment on the hardware side. A different approach is spread spectrum clocking (SSC) that can be used in digital circuits, especially when the operating frequency required by a particular application is generated with a phase locked loop (PLL) circuit. With SSC, a center frequency is modulated in accordance with an appropriate pattern so that the average frequency over time is still the center frequency. In the PLL, a change of frequency can be obtained by adding discrete phase steps to the feedback signal in one or the other of two opposed directions. For example, in a “down spread” the phase of the feedback signal is rotated in an anti-clockwise direction, for “up spread” the phase is rotated in a clockwise direction, and for “center spread” the phase is rotated once in a clockwise and then in an anti-clockwise direction (with reference to a 360° phase diagram of the feedback signal). To add phase steps to the feedback signal in one or the other of the two opposite directions, a phase selector can be used if the oscillator used in the PLL has multiple phase outputs (such as in a ring oscillator, for example). When small phase steps are required, a phase interpolator can be used in conjunction with the phase selector to divide the phase gaps between adjacent phases of the multiple oscillator outputs. Some logic circuitry is provided to control the phase selector and the phase interpolator in accordance with a desired frequency pattern.
A PLL circuit can be used as a frequency synthesizer to generate from an input reference frequency an output frequency determined by the ratio of the dividends used in the input divider and in the feedback divider. When a frequency needed for a particular application cannot be achieved with fixed dividends in the input and feedback dividers, a “fractional-N phase locked loop” is needed. A fractional-N PLL can generate a fractional frequency from a reference frequency. In addition to the conventional input and feedback dividers of the PLL, the feedback loop includes a phase selector or phase aligner capable of adding discrete phase steps to the feedback signal in one or the other of opposite directions. The phase selector is controlled by logic circuitry so that the required number of phase steps is added to the feedback signal in one or the other direction for the desired output frequency of the PLL.
In an application that needs a fractional-N PLL, it would be a major advantage if SSC could be used to reduce the EMI. A possible approach is to interface SSC circuitry with the fractional-N PLL. However, since both approaches, fractional-N and SSC, use the concept of adding phase steps to the feedback signal, conflicting situations can occur. A first situation is when the fractional-N logic and the SSC logic both request a phase step at the same time and in the same direction. In that case, two phase steps are needed, but if both phase steps are made at the same time, the feedback divider experiences a huge phase step and can fail. In addition, a phase shifting circuit is needed that can handle both phase steps at the same time, which is more difficult to achieve. A second situation is when the fractional-N logic and the SSC logic both request a phase step at the same time but in the opposite directions. In such a case, no phase step at all can be needed.